1. Field of the Invention
The present invention relates to a lateral MOSFET, and more particularly to a lateral high breakdown voltage MOSFET with a breakdown voltage between a source and a drain of equal to or more than several tens of volts, or to a semiconductor device including the lateral high breakdown voltage MOSFET.
2. Description of the Related Art
FIG. 9 is a cross sectional view of a p-type lateral high breakdown voltage MOSFET 600 as a first example of a conventional one. The lateral high breakdown voltage MOSFET 600 has a p-type drain diffused layer 614 with a depth of about 1 mm formed by diffusion in a desired region of an n-type semiconductor substrate 601, and an n-well layer 605 formed by diffusion in a similar way on each surface side of the substrate 601 so as to surround an outer periphery of the drain diffused layer 614. In the n-well layer 605, a p-type source diffused layer 609 is formed from on a surface of the substrate 601 in a region apart by a specified distance from the above-described drain diffused layer 614. In the drain diffused layer 614, a p-type drain contact layer 610 is formed on the surface of the substrate 601 in a central region at an approximately equal distance from the boundary with the above-described n-well layer 605.
Moreover, on the surface of the n-well layer 605, a gate oxide film 607 is formed from a top end of the source diffused layer 609 over a top part of the drain-diffused layer 614. On a surface of the drain diffused layer 614, in a region without the drain contact layer 610 and the gate oxide film 607 being formed, there is formed a field oxide film 606.
A gate electrode 608 is formed above the gate oxide film 607 so as to project a part of the field oxide film 606. On the source diffused layer 609 and on the drain contact layer 610, a source electrode 612 and a drain electrode 613 are formed, respectively. The reference numeral 611 denotes an n+ contact layer on the n-well layer 605.
FIG. 10 is a view showing equipotential lines (20V interval) in a reverse-biased state in which a voltage of 100V is applied to the source electrode 612 and the gate electrode 608, and 0V to the drain electrode 613, with the lateral high breakdown voltage MOSFET 600 being turned off. A depletion layer expands on both sides from pn junctions between the p-type drain diffused layer 614 and the n-type semiconductor substrate 601, and the p-type drain diffused layer 614 and the n-well layer 605. In FIG. 10, the equipotential lines of 0V and 100V are approximately equal to respective ends of the depletion layer.
Optimization in the lateral high breakdown voltage MOSFET is to find a structure where a breakdown voltage of an element becomes maximum. Optimization using a RESURF (Reduced Surface Field) structure is known by the reference “High Voltage Thin Layer Device” (IEDM Proceedings, 1979, pp. 238-241).
In the first example of a conventional MOSFET shown in FIG. 9, there is formed on the n-type semiconductor substrate 601 the drain diffused layer 614, which corresponds to a drift region. Therefore, in order to cancel charges of n-type impurities in the n-type semiconductor substrate 601, a total amount of p-type impurities in the drain diffused layer 614 is established as being about 1×1012/cm2 which is made optimum in the above-described reference. Here, a total amount of the above-described impurities can be obtained by integrating a profile of the concentration (cm−3) in the drain diffused layer 614 with respect to a depth of the drain diffused layer 614. Thus, the depletion layer at the reverse-biased state is to extend mainly toward the drain diffused layer 614. Moreover, the gate electrode 608, being formed so as to project onto the field oxide film, provides a structure in which a field plate effect is obtained to make the depletion layer to easily extend into the drain diffused layer 614 for lessening an electric field near the surface thereof.
The lateral high breakdown voltage MOSFET 600 shown in FIG. 9 as the first example of conventional one, has a breakdown voltage of about 110V. To ensure the breakdown voltage, a projection (a distance indicated by “a” in FIG. 9) of the drain diffused layer 614 toward the n-well layer 605 and a channel length (a distance indicated by “b” in FIG. 9) determined by a distance from an end of the source diffused layer 609 to the drain diffused layer 614 are established as being in the order of 6 mm and 3 mm, respectively.
FIG. 11 is a cross sectional view of a second conventional p-type lateral high breakdown voltage MOSFET 700. The lateral high breakdown voltage MOSFET 700 has an n-well layer 705 deeply formed by diffusion in a desired region of a p-type semiconductor substrate 701 on an order of 10 mm from a surface of the semiconductor substrate 701, and a p-type drain diffused layer 714 with a depth of about 1 mm formed by diffusion on the surface side in the n-well layer 705. In the n-well layer 705, a p-type source diffused layer 709 is formed on a side of the substrate 701 surface in a region apart by a specified distance from a boundary of the drain diffused layer 714. In the drain diffused layer 714, a p-type drain contact layer 710 is formed on a side of the substrate surface 701 in a central region at an approximately equal distance from the boundary of the above-described n-well layer 705.
Moreover, on a surface of the n-well layer 705, a gate oxide film 707 is formed on an end of the source diffused layer 709 over a part of the drain diffused layer 714. On a surface of the drain diffused layer 714, in a region without the drain contact layer 710 and the gate oxide film 707 being formed, a field oxide film 706 is formed.
A gate electrode 708 is formed from above the gate oxide film 707 so as to project a part of the field oxide film 706. On the source diffused layer 709 and on the drain contact layer 710, a source electrode 712 and a drain electrode 713 are formed, respectively. The reference numeral 711 denotes an n+ contact layer of the n-well layer 705.
FIG. 12 is a view showing equipotential lines (20V interval) in a reverse-biased state in which a voltage of 100V is applied to the source electrode 712 and the gate 708, and 0V to the drain electrode 713, with the lateral high breakdown voltage MOSFET 700 being turned off. A depletion layer expands on both sides from a pn junction between the p-type drain diffused layer 714 and the n-well layer 705. In FIG. 12, the equipotential lines of 0V and 100V are approximately equal to respective ends of the depletion layer. Moreover, when the p-type semiconductor substrate 701 is set at 0V, the p-type semiconductor substrate 701 and the n-well layer 705 are reverse-biased as shown in FIG. 12 to extend the depletion layer also to the pn junction.
In the second example of a conventional MOSFET shown in FIG. 11, the drain diffused layer 714, which corresponds to a drift region, is formed in the n-well layer 705. Therefore, in order to cancel charges of n-type impurities in the n-well layer 705, a total amount of p-type impurities in the drain diffused layer 714 is established as being about 1×1012/cm2 which is made optimum in the above-described reference. Thus, the depletion layer at the reverse-biased state extends mainly toward the drain diffused layer 714.
Moreover, the gate electrode 708, being formed so as to project onto the field oxide film 706, provides a structure in which a field plate effect is obtained to make the depletion layer to easily extend into the drain diffused layer 714 to lessen an electric field near a surface.
The lateral high breakdown voltage MOSFET 700 shown in FIG. 11, has a breakdown voltage of about 110V. To ensure the breakdown voltage, the projection (a distance indicated by “a” in FIG. 11) of the drain diffused layer 714 toward the n-well layer 705 and a channel length (a distance indicated by “b” in FIG. 11) determined by a distance from an end of the source diffused layer 709 to the drain diffused layer 714, are established as being in an order of 6 mm and 3 mm, respectively.
Next, an explanation will be made about a specific example of applying the lateral high breakdown voltage MOSFET, as described above, to a semiconductor integrated circuit (IC).
As such a specific example, there is a driver IC driving a plasma display panel (hereinafter referred to as PDP).
The PDP, being provided with a flat panel, suited to enlarge a screen, and capable of displaying a high quality image, receives attention as a display device that may substitute a CRT with a growing recent market scale. The PDP is a display in which electrodes on an address side are placed opposite to electrodes on a scanning side to emit light by carrying out charging and discharging with a high voltage of several tens volts or more applied across both opposing electrodes. The address side electrodes and the scanning sides electrodes are formed by several hundreds or more of electrodes to drive, of which driver ICs are used. Output circuits provided in the driver IC are several tens or more circuits. Thus, a number of the driver ICs are used for driving the above-described electrodes.
For example, for the driver IC to drive the address side electrodes, a 100V or more of breakdown voltage between the source and the drain, a ±30 mA of push-pull output, output numbers of 128 bits and the like are required. For a push-pull circuit, there are used high breakdown voltage n MOSFETs on a low potential side and p MOSFETs on a high potential side.
A comparison of the high breakdown voltage n MOSFET with a 30 mA output and a high breakdown voltage p MOSFET with a same output, shows that an area of the high breakdown voltage p MOSFET becomes two to three times the area of the high breakdown voltage n MOSFET, because the high breakdown voltage p MOSFET takes holes as carriers compared with the high breakdown voltage n MOSFET which takes electrons as carriers. A difference in carrier mobility is reflected in the areas of p MOSFET and n MOSFET.
An example of a high breakdown voltage p MOSFET applicable to the driver IC is disclosed in Japanese Patent No. 3198959. In this, element isolation is carried out by using an epitaxial wafer having a buried layer, an arrangement of which is shown in FIG. 13.
FIG. 13 is a cross sectional view of a third example of a conventional p-type lateral high breakdown voltage MOSFET 800. The lateral high breakdown voltage MOSFET 800 is formed with an n-type buried layer 802 in a desired region of a p-type semiconductor substrate 801, and has an n-well layer 805 formed by diffusion from a surface side of an epitaxial layer (not illustrated) formed on the n-type buried layer 802. An n+ wall layer 803 surrounds the outer periphery of the n-well layer 805 and is formed by diffusion down to a depth reaching the n-type buried layer 802. A p-type drain diffused layer 814 with a depth of about 1 mm is formed by diffusion from the surface side in the n-well layer 805. In the n-well layer 805, a p-type source diffused layer 809 is formed from the side of the substrate surface in a region apart by a specified distance from a boundary with the above-described drain diffused layer 814. In the drain diffused layer 814, a p-type drain contact layer 810 is formed from the side of the substrate surface in a central region at an approximately equal distance from the boundary with the above-described n-well layer 805. On the outside of the n+ wall layer 803, a p-well layer 804 is formed to electrically isolate the lateral high breakdown voltage MOSFET 800 from the substrate 801.
Moreover, on the surface of the n-well layer 805, a gate oxide film 807 is formed from an end of the source diffused layer 809 over a part of the drain diffused layer 814. On the surface of the drain diffused layer 814, in a region without the drain contact layer 810 and the gate oxide film 807 being formed, a field oxide film 806 is formed.
A gate electrode 808 is formed from above the gate oxide film 807 so as to project onto a part of the field oxide film 806. On the source diffused layer 809 and on the drain contact layer 810, a source electrode 812 and a drain electrode 813 are formed, respectively.
As described above, by providing the n-type buried layer 802 and the n+ wall layer 803, a current leaking from the element region to the substrate 801 can be reduced. The reference numeral 811 denotes an n+ contact layer to the n-well layer 805.
FIG. 14 is a view showing equipotential lines (20V interval) in a reverse-biased state in which a voltage of 100V is applied to the source electrode 812 and the gate 808, and 0V to the drain electrode 813, with the lateral high breakdown voltage MOSFET 800 being turned off. A depletion layer expands on both sides from a pn junction between the p-type drain diffused layer 814 and the n-well layer 805. In FIG. 14, the equipotential lines of 0V and 100V are approximately equal to respective ends of the depletion layer. Moreover, when the p-type semiconductor substrate 801 is made at 0V, the p-type semiconductor substrate 801 and the n-type buried layer 802 are also reverse-biased, as shown in FIG. 14, to extend the depletion layer from the pn junction.
In the third example of the conventional MOSFET shown in FIG. 13, there is formed in the n-well layer 805 the drain diffused layer 814, which corresponds to a drift region. Therefore, in order to cancel charges of n-type impurities in the n-well 805, a total amount of p-type impurities in the drain diffused layer 814 is established as being about 1×1012/cm2 which is made optimum in the above-described reference. Thus, the depletion layer at the reverse-biased state is to extend mainly toward the drain diffused layer 814.
Moreover, the gate electrode 808, being formed so as to project onto the field oxide film, provides a structure in which a field plate effect is obtained to make the depletion layer to easily extend into the drain diffused layer 814 to lessen an electric field near the surface thereof.
The lateral high breakdown voltage MOSFET 800 shown in FIG. 13 has a breakdown voltage of about 110V. To ensure the breakdown voltage, the projection (a distance indicated by “a” in FIG. 13) of the drain diffused layer 814 toward the n-well layer 805 and a channel length (a distance indicated by “b” in FIG. 13) determined by a distance from an end of the source diffused layer 809 to the drain diffused layer 814, are established as being in an order of 6 mm and 3 mm, respectively.
As has been explained before, in each of the above-described first to third examples of conventional MOSFETs, the RESURF structure is presented in which the depletion layer extends toward the drain diffused layer (614, 714, 814). Another characteristic of each of the lateral high breakdown voltage p MOSFETs is that an electric field strength in the gate oxide film can be suppressed.
As described before, in the reverse-biased state (turned off state) in which the voltage of 100V is applied to the source electrodes (612, 712, 812) and the gates (608, 708, 808), and 0V to the drain electrodes (613, 713, 813), the drain diffused layers (614, 714, 814) and the field oxide films (606, 706, 806), each with a thickness on the order of 800 nm, mainly carry the reverse-bias voltages, which is apparent from the equipotential lines shown in FIG. 10, FIG.12, and FIG. 14.
Meanwhile, the reverse-bias voltages born by the n-well layers (605, 705, 805) and the gate oxide films (607, 707, 807) are 10V or less of the reverse-bias voltages of 100V. Therefore, when the thicknesses of the gate oxide films (607, 707, 807) are made as 25 nm, the electric field strengths in the gate oxide films (607, 707, 807) become 4 MV/cm or less for the above-described 10V to ensure reliability of the gate oxide films.
That is, the above-explained RESURF structure is a structure by which the breakdown voltage between the source and the drain is made maximum to make the gate oxide film carry no reverse-bias voltage in the turned off state. Because of the structure in which no voltage is carried by the gate oxide film, a relatively thin gate oxide film is used.
Problems in the arrangement of carrying most of the source-to-drain voltage with the drain diffused layer and the field oxide film as in the conventional MOSFETs as explained before (RESURF structure) will be explained in the next section.
As has been explained, in the first to third examples of conventional MOSFETs, the RESURF structure is employed to optimize a structure to make the breakdown voltage maximum of an element. Therefore, a total amount of the p-type impurities in each of the drain diffused layers (614,714, 814) becoming drift regions is established as being in the order of 1×1012/cm2. Moreover, each of the projections of the drain diffused layers (614, 714, 814) toward the n-well layers (605, 705, 805) is established as being in the order of 6 mm.
Such RESURF structure is an effective approach to enhance a breakdown voltage of an element. On the other hand, the structure has a problem of providing high on-resistance.
First, a total amount of impurities in the drain diffused layer is low. Namely, with the total amount of impurities in the drain diffused layer as being on the order of about 1×1012/cm2, the resistance of the drain diffused layer is increased. A drain resistance occupies a major fraction of the on-resistance components of the lateral high breakdown voltage MOSFET with the RESURF structure. The drain resistance occupies about 90%. A channel resistance is on the order of 10%. The drain resistance is the resistance of the drain diffused layer with sheet resistance of the drain diffused layer given as about 12 kΩ/square in the above-described examples of the conventional MOSFETs.
Second, the projected length of the drain diffused layer is long. Namely, in order to ensure a breakdown voltage between the source and the drain, the length has been established as being in the order of 6 mm in the above-described examples. As the length becomes longer, the on-resistance increases.
To reduce the on-resistance, an impurity concentration in the drain diffused layer can be increased. The increased concentration, however, causes a problem of making the drain diffused layer hard to become depleted. In addition, the drain diffused region, being formed with a shallow diffused depth of about 1 mm, enhances the electric field at the cylindrical portion as the impurity concentration is increased, which causes a problem of reducing the breakdown voltage between the source and the drain.
Therefore, the impurity concentration in the drain diffused layer cannot be simply increased. Hence, the impurity concentration in the drain diffused layer is inevitably made lower to cause a problem of increasing the on-resistance.